Intel Unveils 48-Core Single-Chip Cloud Computer
Posted by amcanty on December 10, 2009
Wednesday, December 02, 2009 – by Dave Altavilla and Marco Chiappetta
“Earlier today in a San Francisco press briefing Intel Chief Technology Officer, Justin Rattner took the wraps off a proof of concept and experimental product that Intel dubbed a “Single-Chip Cloud Computer”. The objective this chip was designed to address is the huge opportunity that exists to reduce power consumption and space in the data center, a very real place, rather than mythical, where “the cloud” really exists and increasing user demand for online services continues to chew up bandwidth, processing resources and storage like there is no tomorrow.
The Intel Single-chip Cloud Computer or “SCC” for short, is what Intel likes to call a “many core” CPU but actually consists of a 48-core implementation using 45nm process technology. The cores on the chip are networked together in a packet-based router mesh network, where the nodes (or individual cores) behave quite similarly to a network cloud but on a monolithic silicon chip level. There are, in fact, 24 “routers” to connect and manage all 48 cores and the chip also contains an additional 4 DDR3 memory controllers to feed the network data, with 64GB total addressable memory space per SCC chip.”
Intel has produced a short video that talks to some of the experimental chip’s features and capabilities and potential uses in the market. The chip was designed as part of Intel’s Tera-Scale research initiative as a concept vehicle for highly threaded software research. Essentially, the single-chip was designed to resemble a cluster of compute nodes which can communicate with another compute node using packet-based network technology.
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Despite the 48-core chip’s relatively complexity, Intel was able to get the processor’s power envelope into the 25 – 125w range, depending on the workload and number of active cores. The cores are arranged in such a way that individual clusters, or islands as Intel calls them, can operate at different frequencies and voltage levels. There are 24 tiles on the chip consisting of dual execution cores, each with its own L2 cache.
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